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.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 1 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ fuji power supply control ic power factor correction FA5612 / fa5613 application note ?11-4 fuji electric co.,ltd.
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 2 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 1. this data book contains the product specifications, characteristics, data, materials, and structures as of apr. 2011. the contents are subject to change without notice for specification changes or other reasons. when using a product listed in this data book, be sure to obtain the latest specifications. 2. all applications described in this data book exemplify the use of fuji?s products for your reference only. no right or license, either express or implied, under any patent, copyright, trade secret or other intellectual property right owned by fuji electric co., ltd. is (or shall be deemed) granted. fuji makes no representation or warranty, whether express or implied, relating to the infringement or alleged infringement of other?s intellectual property rights which may arise from the use of the applications described herein. 3. although fuji electric is enhancing product quality and reliability, a small percentage of semiconductor products may become faulty. when using fuji electric semiconductor products in your equipment, you are requested to take adequate safety measures to prevent the equipment from causing a physical injury, fire, or other problem if any of the products become faulty. it is recommended to make your design fail-safe, flame retardant, and free of malfunction. 4. the products introduced in this data book are intended for use in the following electronic and electrical equipment which has normal reliability requirements. ? c o m p u t e r s o a e q u i p m e n t ? c o m m u n i c a t i o n s e q u i p m e n t ( t e r m i n a l d e v i c e s ) ? m e a s u r e m e n t e q u i p m e n t ? m a c h i n e t o o l s a u d i o v i s u a l e q u i p m e n t ? e l e c t r i c a l h o m e a p p l i a n c e ? p e r s o n a l e q u i p m e n t ? i n d u s t r i a l r o b o t s e t c . 5. if you need to use a product in this data book for equipment requiring higher reliability than normal, such as for the equipment listed below, it is imperative to contact fuji electric to obtain prior approval. when using these products for such equipment, take adequate measures such as a backup system to prevent the equipment from malfunctioning even if a fuji?s product incorporated in the equipment becomes faulty. ? t r a n s p o r t a t i o n e q u i p m e n t ( m o u n t e d o n c a r s a n d s h i p s ) ? t r u n k c o m m u n i c a t i o n s e q u i p m e n t ? t r a f f i c - s i g n a l c o n t r o l e q u i p m e n t ? g a s l e a k a g e d e t e c t o r s w i t h a n a u t o - s h u t - o f f f e a t u r e ? e m e r g e n c y e q u i p m e n t f o r r e s p o n d i n g t o d i s a s t e r s a n d a n t i - b u r g l a r y d e v i c e s ? s a f e t y d e v i c e s 6. do not use products in this data book for the equipment requiring strict reliability such as (without limitation) ? s p a c e e q u i p m e n t ? a e r o n a u t i c e q u i p m e n t ? a t o m i c c o n t r o l e q u i p m e n t ? s u b m a r i n e r e p e a t e r e q u i p m e n t ? m e d i c a l e q u i p m e n t 7. copyright ? 1995 by fuji electric co., ltd. all rights reserved. no part of this data book may be reproduced in any form or by any means without the express permission of fuji electric. 8. if you have any question about any portion in this data book, ask fuji electric or its sales agents before using the product. neither fuji nor its agents shall be liable for any injury caused by any use of the products not in accordance with instructions set forth herein. warning
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 3 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ contents 1. description .................... 4 2. features .................... 4 3. outline .................... 4 4. types of FA5612/13 .................... 4 5. block diagram .................... 5 6. pin assignment .................... 5 7. ratings and characteristics .................... 6~10 8. characteristics curves .................... 11~13 9. outline of circuit operation .................... 14 10. description of each circuit block .................... 15~19 11. descriptions of use for each pin .................... 20~26 12. advice for design .................... 27~29 13. example of application circuit .................... 30 note ? t h e c o n t e n t s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e f o r s p e c i f i c a t i o n c h a n g e s o r o t h e r r e a s o n s . ? p a r t s t o l e r a n c e a n d c h a r a c t e r i s t i c s a r e n o t d e f i n e d i n a l l a p p l i c a t i o n d e s c r i b e d i n t h i s d a t e b o o k . when design an actual circuit for a product, you must determine parts tolerance and characteristics for safe and economical operation.
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 4 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 1. description FA5612/13 is control ic for power factor correction converter. it realizes low power consumption by using high voltage cmos process. thanks to a average current control, a stable operation is obtained, whereby a power factor of 99% or more is easily available. dc output voltage is controlled under a wide range of load from rated to no load. further, a unique switching frequency diffusion function incorporated simplifies the line filter. 2. features ? u n i q u e s w i t c h i n g f r e q u e n c y d i f f u s i o n f u n c t i o n i n c o r p o r a t e d ? s e l e c t a b l e s w i t c h i n g f r e q u e n c y : d i f f u s e o r f i x ( 6 0 k h z , 6 5 k h z ) ? h i g h - p r e c i s i o n o v e r c u r r e n t p r o t e c t i o n : 0 . 5 v 5 % ? n o a u d i b l e n o i s e a t s t a r t u p b y d y n a m i c o v p c i r c u i t ? l o w c u r r e n t c o n s u m p t i o n b y h i g h v o l t a g e c m o s p r o c e s s operating : 2ma (typ.) ? e n a b l e d t o d r i v e p o w e r m o s f e t d i r e c t l y . output peak current, source : 1.5a, sink : 1.5a. ? o p e n / s h o r t p r o t e c t i o n a t f e e d b a c k ( f b ) p i n ? u n d e r - v o l t a g e l o c k o u t FA5612 : 9.6v on / 9v off fa5613 : 13v on / 9v off ? 8 - p i n p a c k a g e : s o p - 8 , d i p - 8 3. outline sop-8 dip-8 4. type of FA5612/13 type startup threshold package FA5612n 9.6v (typ.) sop-8 FA5612p 9.6v (typ.) dip-8 fa5613n 13v (typ.) sop-8 5 8 4 1 3 . 4 0.25 0.1 0.5 0.1 2.54 2.54 3=7.62 7.6 0 1 5 3 . 5 m a x . 6 . 5 9.4 4 . 5 m a x .
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 5 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 5. block diagram 6. pin assignment pin no. pin symbol function description 1 fb voltage feedback input inverting input for voltage error amplifier. input terminal of converter output voltage. 2 vcmp voltage loop compensation output of voltage error amplifier. phase compensator circuit is connected. *2 3 vdet ac voltage input input terminal for sinusoidal ac input voltage waveform. 4 is current sense input input terminal for inductor current signal. 5 icmp current loop compensation output of current error amplifier. phase compensator circuit is connected. *2 6 gnd ground ground 7 out output output for driving a power mosfet. 8 vcc power supply power supply for ic control circuit and output circuit. *1 *1 connect the capacitor. *2 connect capacitor and the resistor. vcc out gnd icmp fb vcmp is vdet FA5612n 8 7 6 5 1 2 3 4
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 6 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 7. ratings and characteristics the contents are subject to change without notice. when using a product, be sure to obtain the latest specifications. stress exceeding absolute maximum ratings may malfunction or damage the device. ?+? shows sink and ??? shows source in current prescription. (1) absolute maximum ratings item symbol ratings unit total power supply and zener current (vcc) *1 icc+iz 15 ma icc > 4.8ma vcc1 - 0.3 to 28 v supply voltage (vcc) *1 icc < 4.8ma vcc2 - 0.3 to self limiting v output voltage (out) *4 vout - 0.3 to vcc + 0.3 v output current (out) *1 iout - 1500 to 1500 ma output peak current (out) *2 iout_pk self limiting ma input voltage (fb , vdet) vfb,vvdet - 0.3 to 5.0 v i n p u t c u r r e n t ( f b , v d e t ) * 3 i f b , i v d e t - 1 0 0 t o 1 0 0 a input voltage (vcmp) vvcmp - 0.3 to 5.0 v input current (vcmp) *3 ivcmp - 0.5 to 30 ma input voltage (icmp) vvcmp - 0.3 to 5.0 v input current (icmp) *3 iicmp - 0.2 to 30 ma input voltage (is) vis - 5.0 to 1.0 v i n p u t c u r r e n t ( i s ) * 3 i i s - 3 0 0 t o 1 0 0 a dip-8 pd1 800 mw power dissipation sop-8 pd2 400 mw operating junction temperature tj - 30 to +150 c storage temperature tstg - 40 to +150 c *1 must not exceed power dissipation. *2 period exceeding 1500ma must be 100ns or less. *3 when the pin current flows continuously for 100ns or more. *4 the period of 100ns (dead time period) when the voltage of the terminal out changes low ? high is out of the question. maximum dissipation curve *5 jedec standard test board package thermal resistor *5 j - a = 3 1 2 c / w , j - c = 7 2 c / w ( s o p - 8 ) j - a = 1 5 6 c / w , j - c = 5 0 c / w ( d i p - 8 ) -40 25 105 150 400mw(sop) 800mw(dip) S p ? ta( ) m a x i m u m d i s s p a t i o n p d ( m w ) ambience temperature ta (c)
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 7 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ (2) recommended operating conditions item symbol min. typ. max. unit supply voltage vcc 10 18 26 v vdet pin input voltage vvdet 0 - 2.4 v vdet pin peak input voltage vpvdet 0.54 - 2.4 v is pin voltage vis - 1.0 - 0.5 v i s p i n c o n n e c t i o n n o i s e f i l t e r r e s i s t a n c e r i s f - - 1 0 0 ambiance temperature in operation ta -40 - 105 item symbol resistance accuracy temperature characteristics frequency diffusion r g 1 4 . 7 k 5 % 2 0 0 p p m / c 1 2 k 2 % 2 0 0 p p m / c 65khz fixed rg2 1 3 k 5 % 2 0 0 p p m / c frequency setting resistance *2 6 0 k h z f i x e d r g 3 2 7 k 5 % 2 0 0 p p m / c * 2 ) f o r c o n n e c t i o n i n f i g . 2 , r o r a n g e : 0 t o 1 0 0 fig.1 is pin-connected filter resistance fig.2 frequency setting resistance driver rg out 7 ro 8 vcc 6 gnd
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 8 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ (3) electrical characteristics (unless otherwise specified, vfb=2.5v, vvcmp=2.5v, vvdet=0v, vis=0v, vicmp=2.0v, v c c = 1 8 v , r g = 4 . 7 k , t j = 2 5 c ) ?+? shows sink and ??? shows source in current prescription. voltage amplifier (fb, vcmp pin) item symbol condition min. typ. max. unit voltage feedback input threshold vref ivcmp = 0ua 2.450 2.500 2.550 v line regulation regline vfb = vref, vcc = 10v to 26v - 12.5 - 12.5 mv temperature stability vrefdt vfb = vref, tj = - 30c to 150c - 0.5 - 0.5 mv/c transconductance gmv vfb = vref 0.3v 70 90 120 mho ivsrc source : vfb = 1.5v - 70 - 50 - 30 a vcmp output current ivsnk sink : vfb = 3.5v 30 50 70 a vcmp output h voltage vvcmph vfb = 1.5v - - 5.5 v vcmp transient response output current iresp source : vfb = 1.5v - 170 - 140 - 110 a vcmp transient response detection voltage vresp 0.902 *vref 0.940 *vref 0.978 *vref v current amplifier (icmp pin) item symbol condition min. typ. max. unit transconductance gmc vis= - 0.2v to - 0.4v, vvdet *1 40 60 80 mho icsrc source : vvdet = 3.5v - 70 - 50 - 30 a output current icsnk sink : vis = -2.0v, 30 50 70 a icmp clamp voltage vclamp vicmp = 3.0v i i c m p m a x = 3 2 0 a 2.6 2.7 2.9 v *1 vvdet is for when vis = -0.3v, iicmp = 0a multiplier item symbol condition min. typ. max. unit v d e t i n p u t b i a s c u r r e n t i v d e t v v d e t = 0 v , - 1 . 5 - 0 . 5 0 a vcmp threshold voltage vthvcmp vvdet = 2.4v 0.3 0.5 0.7 v output voltage coefficient k v v c m p = 1 v , i i c m p = 0 a vvdet = 0.3v, 1.3v vis = 0.1v to -0.2v 0.5 0.70 0.95 - oscillator item symbol condition min. typ. max. unit frequency diffusion (reference frequency) fswref vvdet = 0.88v, vis = - 0.18v, vvcmp *1, iicmp = 0a, 54 60 66 khz frequency temperature stability fswrefdt vvdet = 0.88v, vis = - 0.18v, vvcmp *1, iicmp = 0a,tj=-30c to 125c -0.06 - 0.06 khz/c frequency diffusion (maximum frequency) fswmax vvcmp = 0v, vvdet = 2.4v 64 68 70 khz frequency diffusion, (minimum frequency) fswmin vvcmp = 0v, vvdet = 0v 50 52 55 khz fixed frequency 1 fsw1 vout2 < vout 54 60 66 khz fixed frequency 2 fsw2 vout1 < vout < vout2 58.5 65 71.5 khz maximum duty cycle dmax vvdet = 2.4v, icmp no connect 91 94 97 % *1 vvcmp is for when vvdet = 0.88v, vis = -0.18v, iicmp = 0a
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 9 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ overvoltage protection comparator (fb pin) item symbol condition min. typ. max. unit static ovp threshold voltage vsovp vfb = 2.5v to 2.9v, vvcmp = 0v, vvdet = 0v 1.070*vref 1.090*vref 1.105*vref v hysteresis vsovphys vfb = 2.9v to 2.5v, vvcmp = 0v, vvdet = 0v 0.005*vref 0.020*vref 0.040*vref v static ovp temperature stability vsovpdt vfb = 2.5v to 2.9v, vvcmp = 0v vvdet = 0v, tj= -30c to 125c -0.0001*vref - 0.0001*vref v/c dynamic ovp threshold voltage vdovp vfb = 2.5v to 2.8v, vvcmp = 1v, vvdet = 2v 1.025*vref 1.050*vref 1.075*vref v S ovp S ovp vsovpn -vdovp 50 95 140 mv fb short detection comparator (fb pin) item symbol condition min. typ. max. unit input threshold voltage vthfb vfb = 0v to 1v, vvcmp = 0v 0.1 0.3 0.5 v p u l l - d o w n r e s i s t a n c e r f b v f b = 2 . 5 v 2 . 0 2 . 5 3 . 0 m overcurrent detection comparator (is pin) item symbol condition min. typ. max. unit is offset voltage visof vvdet = -0.25v, vvcmp = 0.6v 0 30 60 mv is pin voltage vis_054 vvdet = 0.54v, vvcmp = 5.0v - 0.43 - 0.38 - 0.33 v vocpl vvdet max = 1.2v, vvdet min = 0v, fvdet = 50khz, dvdet=50% - 0.525 - 0.50 - 0.475 v is threshold voltage vocph vvdet max = 1.8v, vvdet min = 0v, fvdet = 50khz, dvdet=50% - 0.432 - 0.40 - 0.368 v is threshold voltage temperature characteristics vocpldt vvdet max = 1.2v, vvdet min = 0v, fvdet = 50khz dvdet=50%,vis = -0.4v to -0.6v tj=-30c to 125c - 0.1 - 0.1 mv/c vvdeth vvdet max = 1.2v, to 1.8v vvdet min = 0v, fvdet = 50khz dvdet=50%,vis= -vocpl + 0.05v 1.54 1.60 1.66 v vdet threshold voltage vvdetl vvdet max = 1.8v to 1.0v, vvdet min = 0v, fvdet = 50khz dvdet=50%,vis= -vocpl + 0.05v 1.30 1.35 1.40 v is threshold change voltage vvdets vvdet max = 1.8v vvdet min = 0v, fvdet = 50khz dvdet=50%,vis= -vocpl + 0.05v 0.25 0.30 0.35 v blanking time *1 tblk vis= -0.6v 300 450 600 ns delay time tdly vis = vocpl + 30mv to-1.0v pulse signal 200 350 500 ns i n p u t b i a s c u r r e n t i i s v v c m p = 0 v , v i s = 0 v - 1 7 0 - 1 2 0 - 7 0 a *1 includes delay time output (out pin) item symbol condition min. typ. max. unit output voltage (l) voutl vfb = 0v, vvcmp = 0.3v, vicmp = 3v to 2v, sink : iout = 100ma - 0.5 1.0 v output voltage (h) vouth vvcmp = 0.3v, vicmp = 3v to 2v, source : iout = - 100ma 15.5 16.5 - v output rise time tr c l = 1nf - 50 - ns output fall time tf c l = 1nf - 50 - ns
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 10 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ frequency setting (out pin) item symbol condition min. typ. max. unit d e t e c t i o n c u r r e n t i s t a t e t j = - 3 0 c t o 1 2 5 c 3 4 4 0 4 6 a vout1 tj=-30c to 125c 260 310 390 mv out threshold voltage vout2 tj=-30c to 125c 700 760 830 mv frequency setting time *1 tset vvcmp = 0v, vicmp = 0v vfb = 2v 4.1 5.9 7.7 ms detection time *2 tdet vvcmp = 0v, vicmp = 0v vffb= 2v 4 2 0 5 3 0 6 4 0 s *1: time elapsing until detection current is outputted from out pin after removal of uvlo *2: period during which detection current is outputted from out pin low voltage protection (vcc pin) item symbol condition min. typ. max. unit FA5612: vcc= 8v to 11v 8.6 9.6 10.6 v on threshold voltage vccon fa5613: vcc= 11v to 15v 11.5 13 14.5 v off threshold voltage vccoff vcc= 11v to 7v 8.0 9.0 10.0 v FA5612 0.4 0.6 0.8 v hysteresis vcchys fa5613 3.5 4.0 4.5 v all devices (vcc pin) item symbol condition min. typ. max. unit start-up current istart vcc = 8v, vvcmp = 0v vicmp =0v 70 90 110 a operating current icc out pin no load - 2.0 4.0 ma off time current iccoff out pin no load vvcmp=0v - 1.8 3.8 ma standby current istb vcc = 18v, vfb = 0v vvcmp=0v, vicmp =0v 80 110 180 a
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 11 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 8. characteristics curves ( u n l e s s o t h e r w i s e s p e c i f i e d , v f b = 2 . 5 v , v v c m p = 2 . 5 v , v v d e t = 0 v , v i s = 0 v , v i c m p = 2 . 0 v , v c c = 1 8 v , r g = 4 . 7 k , t j = 2 5 c ) voltage error amplifier: input threshold (vref) vs. supply voltage (vcc) 2.45 2.47 2.49 2.51 2.53 2.55 10 15 20 25 30 vcc [v] v r e f [ v ] voltage error amplifier: input threshold (vref) vs. junction temperature (tj) 2.45 2.47 2.49 2.51 2.53 2.55 -50 0 50 100 150 tj [c] v r e f [ v ] oscillator: reference, maximum, minimum frequency (fswref, fswmax, fswmin) vs. supply voltage (vcc) 50 54 58 62 66 70 10 15 20 25 30 vcc [v] f s w r e f , f s w m a x , f s w m i n [ k h z ] fswmax fswref fswmin oscillator: reference, maximum, minimum frequency (fswref, fswmax, fswmin) vs. junction temperature (tj) 45 50 55 60 65 70 75 -50 0 50 100 150 tj [c] f s w r e f , f s w m a x , f s w m i n [ k h z ] fswmax fswref fswmin oscillator: fixed frequency 1,2 (fswr1, fsw2) vs. supply voltage (vcc) 50 54 58 62 66 70 10 15 20 25 30 vcc [v] f s w 1 , f s w 2 [ k h z ] fsw2(65khz) fsw1(60khz) oscillator: fixed frequency 1,2 (fswr1, fsw2) vs. junction temperature (tj) 45 50 55 60 65 70 75 -50 0 50 100 150 tj [c] f s w 1 , f s w 2 [ k h z ] fsw2(65khz) fsw1(60khz) oscillator: maximum duty cycle (dmax) vs. junction temperature (tj) 90.0 91.0 92.0 93.0 94.0 95.0 96.0 97.0 98.0 -50 0 50 100 150 tj [c] d m a x [ % ] overcurrent detection: is threshold voltage (vocpl, vovph) vs. junction temperature (tj) -0.53 -0.51 -0.49 -0.47 -0.45 -0.43 -0.41 -0.39 -0.37 -50 0 50 100 150 tj [c] v o c p l , v o c p h [ v ] vocph vocpl
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 12 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ current error amplifier: output current (iicmp) vs. is pin voltage (vis) -60 -40 -20 0 20 40 60 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 vis [v] i i c m p [ u a ] current error amplifier: output current (ivcmp) vs. fb pin voltage (vfb) -60 -40 -20 0 20 40 60 1.0 1.5 2.0 2.5 3.0 3.5 4.0 vfb [v] i v c m p [ u a ] overvoltage comparator: dynamic/static ovp (vdovp/vref, vsovp/vref) vs. junction temperature (tj) 1.025 1.035 1.045 1.055 1.065 1.075 1.085 1.095 1.105 -50 0 50 100 150 tj [c] v d o v p / v r e f , v s o v p / v r e f vdovp vsovp out pin: output voltage(l) (voutl) vs. supply voltage (vcc) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 10 15 20 25 30 vcc [v] v o u t l [ v ] out pin: output voltage(h) (vouth) vs. supply voltage (vcc) vcc - vouth 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 10 15 20 25 30 vcc [v] v c c - v o u t h [ v ] multiplier: is pin voltage (vis) vs. vdet pin voltage (vvdet) -600 -500 -400 -300 -200 -100 0 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 vvdet [v] v i s [ v ] vvcmp=0.6v vvcmp=1.0v vvcmp=1.5v vvcmp=2.0v vvcmp=3.0v
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 13 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ current consumption: operating current (icc) vs. supply voltage (vcc) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 5 10 15 20 25 30 vcc [v] i c c [ m a ] FA5612 current consumption: operating current (icc) vs. supply voltage (vcc) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 5 10 15 20 25 30 vcc [v] i c c [ m a ] fa5613 under voltage lockout: vcc threshold voltage (vccon, vccoff) vs. junction temperature (tj) 8.5 9.5 10.5 11.5 12.5 13.5 14.5 -50 0 50 100 150 tj [c] v c c o n , v c c o f f [ v ] vccoff vccon fa5613 current consumption: operating current (icc) vs. junction temperature (tj) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 0 50 100 150 tj [c] i c c [ m a ] under voltage lockout: vcc threshold voltage (vccon, vccoff) vs. junction temperature (tj) 8.5 8.7 8.9 9.1 9.3 9.5 9.7 9.9 10.1 10.3 10.5 -50 0 50 100 150 tj [c] v c c o n , v c c o f f [ v ] vccoff vccon FA5612 ?R` ^ R vresp vs. tj 0.925 0.930 0.935 0.940 0.945 0.950 0.955 0.960 0.965 0.970 -50 0 50 100 150 tj [ ] v r e s p [ v / v ] ^ R ` S ovp vs. tj 50 60 70 80 90 100 110 120 130 140 -50 0 50 100 150 tj [ ] S o v p [ m v ] current error amplifier. output current (iicmp) vs. junction temperature (tj) overvoltage comparator ?? ovp vs. junction temperature (tj)
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 14 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 9. outline of circuit operation FA5612/fa5613 are controllers for power factor correction converter using boost topology. these ic are designed for the ccm mode operation with the average current control. the operations, (1) switching and (2) power factor collection, are explained as below with the simplified circuit diagram shown in fig.1. (1) switching operation fig. 2 outlines the waveform of each part of switching operation at a steady state. the operation is as follows. i. set signal of switching frequency outputted from the oscillator sets rs. f/f, whereby out pin voltage goes high, thus turning on q1. ... (t1) ii. q1 turned on raises the current of l1. the current of l1 is converted by rs connected on gnd side into a voltage and is inputted to is pin (vis). vis is compared by current amplifier (cur. amp) with reference voltage that is obtained via arithmetic output by multiplier (mul) from input voltage monitoring vdet and vcmp that is obtained by feedback from output and error amplification. current amplifier output (icmp) is compared by pwm comparator (pwm. comp) with slope waveform outputted from oscillator and, as soon as it attains the reference value, reset signal enters rs. f/f, thereby turning off q1. ... (t2) iii. q1 turned off inverts the voltage of l1. while a current is being fed to the output via d1, the current of l1 reduces. set signal outputted from internal oscillator transfers the circuit to the next switching cycle. ... (t1) (2) power factor correcting operation the voltage at vcmp pin that constitutes output of error amplifier (err.amp) is almost dc voltage at a steady state, because of connected phase compensation capacitance. this voltage is inputted to multiplier. another input to multiplier is a waveform obtained by rectifying ac input voltage. a multiplier multiplies these two of input and outputs a sinusoidal wave proportional to ac input voltage. this outputted sinusoidal voltage waveform is applied as a reference inductor current to current amplifier (cur.amp). therefore, the inductor current's mean value forms a sinusoidal waveform. the current of inductor l1 is deprived of switching ripples by c1 and is turned into a average current. thus, the current from ac input voltage becomes practically sinusoidal, thus improving the power factor. fig.2 waveforms of switching operation (outline) fig.1 block diagram of operating circuit fig.4 power factor corrected waveform c1 removes ripples caused by switching from current mul 1 3 4 2 err.amp vcmp vdet is fb ac cur.amp q1 rs d1l1 c1 v t ( ) v t ( ) v t ( dc) t i v il detectorv t 5 t icmp fig.3 aspects of waveforms at different parts almost dc sinusoidal sinusoidal
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 15 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 10. description of each circuit block (1) frequency setting circuit the switching frequency is selectable out of 3 modes by resistance rg connected between out and gnd pins. ? m o d e 1 : f r e q u e n c y d i f f u s i o n 5 0 k h z t o 7 0 k h z ? m o d e 2 : f i x e d f r e q u e n c y 1 6 5 k h z ? m o d e 3 : f i x e d f r e q u e n c y 2 6 0 k h z the status setting is completed after fb short detection or uvlo are canceled. the switching operation will start after this completion. therefore, the mode will not change while operating. as an example, the operation of frequency setting which is in case of a cancellation of uvlo is shown in fig. 6. ic starts to operate after vcc exceeds vccon. then after 5.9ms, the out pin outputs current istate (40ma (typ.)) during 530us. the current generates a voltage at out pin because external resistors (ro and rg) are connected to out pin. the frequency setting is done with based on this out pin voltage. the internal circuits start switching operation after frequency setting. likewise, in case of cancellation of fb short detection, 5.9ms after the cancellation, a current is outputted from out pin for 530us, and then switching starts. out pin has in its inside reference voltages of 2 levels, or vout1 (310mv (typ.)) and vout2 (760mv (typ.)) to select a frequency, a reference voltage is compared with out pin voltage while current istate is flowing. the relationship is as follows. out pin voltage out pin < vout1 vout1 < out pin < vout2 vout2 < out pin mode mode1 mode2 mode3 frequency frequency diffusion fixed frequency 65khz fixed frequency 60khz (2) oscillator oscillator outputs two signals. one is a set signal to flip-flop for setting the out pin to vcc level. another is a sawtooth signal for pwm comparison. the oscillation frequency is set by frequency setting circuit to either the frequency diffusion mode or 2 kinds of the fixed frequency mode. (2-1) frequency diffusion when the frequency diffusion mode is selected, the frequency changes between 50 and 70 khz according to the input/output status of pfc power supply. the optimized frequency diffusion based on input/output status realizes a low noise operation with a wide operation range. osc block determines the frequency based on vdet pin input voltage and multiplier block output voltage. when the phase angle is range of 0 to 30 or 150 to 180 approximately, the frequency rises in proportion to vdet pin voltage. when it is range of 30 to 150 approximately, the frequency is reversely proportional to the multiplier output. (fig.8) when the multiplier output is high like when pfc output current is large, the frequency drop is bigger. and it is small in case of reverse situation. the approximate frequency (fsw_b) is given by an equation below when the phase angle is range of 30 to 150. fsw_b = 75 ? 71.4 (is pin voltage) [khz] fig.5 frequency setting circuit rg end ? _ ? driver osc state set out 7 ro uvlo_l istate end signal: each block starts up fig.6 frequency setting sequence r g ? vcc istate end out 0v 5.9ms istate*(ro+rg) vcmp 0.5v 530us vccon tset tdet internal power supply end signal time fig.7 block diagram for oscillator area 2 vdet vcmp osc 3 multiplier cur.amp. il detector pwm comp. f.f. set set signal
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 16 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ (2-2) maximum and minimum frequencies in frequency diffusion mode as stated above, the switching frequency in the frequency diffusion mode depends on vdet pin or multiplier output voltage within maximum and minimum frequencies determined. however, maximum or minimum frequency may never appear under some conditions while 1/2 of ac cycle. (3) error amplifier the error amplifier is a circuit for controlling pfc output to a certain level. this ic adopts a transconductance amplifier. the non-inverting input terminal for the error amplifier is connected to the internal reference voltage of 2.5 v (typ.) the inverting input terminal (fb) receives the output voltage, usually resistively divided, from power factor correction converter. for fb open detecting function, this terminal is c o n n e c t e d t o a p u l l - d o w n r e s i s t o r o f 2 . 5 m i n s i d e t h e i c . e r r o r a m p l i f i e r output (vcmp) is connected to multiplier (mul) to control the inductor current. output voltage vout of power factor correction converter usually contains a lot of ripples of double the ac line frequency (50 or 60 hz). when ripples corresponding to double the ac frequency appear excessively on the error amplifier output, power factor correction converter will not operate stably. so, a capacitor and resistor network is connected between pin 2 (vcmp) which is output of the error amplifier and gnd for phase compensation. increasing the capacitance in the phase compensation network improves the power factor, but the transient responsivity becomes slow. the error amplifier in FA5612/13 has a function of improving the transient responsivity. when the load has suddenly become so heavy, the fb pin voltage drops much. if lowered fb pin voltage is below transient response detection voltage (vresp), the transient response correction circuit increases output current of error amplifier up to the transient response output current (iresp). thus, the vcmp pin voltage rises quickly to increase the output current and suppress the output voltage drop. (4) overvoltage protection circuit (ovp) this is a circuit for limiting the voltage when the output voltage of power factor correction converter has exceeded the setting. when converter is started up or when the load has suddenly changed, the converter output voltage may rise beyond the setting. in such a case, ovp circuit prevents an over voltage and protects the converter. FA5612/13 has a dynamic ovp function and a static ovp function. the dynamic ovp function restricts the multiplier gain depending on rising of fb pin voltage while fb pin voltage exceeds 2.5 v. the static ovp function makes out pulses stop while fb pin voltage exceeds 1.09 time of the reference voltage. in normal operation, the fb pin voltage is 2.5 v that is almost the same as the reference voltage of error amplifier. when the fb pin voltage exceeds 2.5 v by startup or a sudden change of load, the dynamic ovp function reduces output current by lowering the multiplier gain. then, if the fb pin voltage still rises and exceeds the reference voltage of a static ovp function, FA5612/13 stops the output pulses. out pulses stopped by the overvoltage protection are resumed as soon as the output voltage lowers back to 1.07 times the reference voltage. (5) fb short/open detector on the circuit of fig. 10, if the fb pin voltage is zero because of r2 short or r1 open, the error amplifier can not control the constant voltage. therefore, the output voltage rises abnormally. in such a case, the overvoltage protection circuit could not operate because the output voltage detection is faulty. 1 vcmp sp erramp vref(2.5v) vthfb(0.3v) fb vout r1 r2 open/short c3 2.5m o.v.p static c4 c5 r3 2 mul fig.9 error amplifier and overvoltage protection circuit 30 60 90 120 150 180 50khz 70khz vdet R I \ I fsw fig.8 oscillation frequency vs. phase angle region subject to multiplier output region subject to vdet voltage phase angle fig.10 fb open/short detector 7 1 out fb 2.5m ? ? 0.3v sp vfb=0v r2 r1 ` ` vo output stop detect open short
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 17 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ to avoid such inconvenience, the ic has fb short detector. the circuit consists of reference voltage of 0.3 v (typ.) and comparator (sp). when the fb pin input voltage has dropped below 0.3 v because of r2 short or r1 open, the output of comparator (sp) is inverted to stop the ic output. the pfc converter outputs a voltage corresponding to the input voltage even before startup because of the boost topology. that is why, this function never operate as long as the converter is normal. in case of an open failure of the fb pin FA5612/13 stops the output pulse b y t h i s f u n c t i o n b e c a u s e a p u l l - d o w n r e s i s t o r o f 2 . 5 m i n s i d e t h e i c i s connected to the fb pin. if the fb pin voltage has dropped to almost zero, the ic output will stop. when the fb pin voltage returns normal then, out pulses will reappear. (6) multiplier multiplier is the circuit for controlling the input current as the sinusoidal wave forms the same as input voltage. an input is connected to vdet pin and is inputted the dividing voltage after being rectified from ac input voltage. the other input is connected to error amplifier output (vcmp). normally, the error amplifier output is almost dc, and multiplier outputs a sinusoidal waveform voltage whose amplitude changes according to the error amplifier output voltage. the multiplier output constitutes a reference for current comparator to control the input current to a sinusoidal waveform (fig. 11). it usually makes mul pin peal voltage set to 0.65 to 2.4 v in the all ac input range. the voltage obtained by rectifying the ac input voltage contains many noises attributable to switching by q1. to eliminate the influence by the noise, filtering capacitance c6 is provided usually. (7) current detector il. detector inverts and amplifies a voltage obtained by voltage-current conversion via current detecting resistance rs of the inductor current. current amplifier (cur. amp) is error amplifier that composes a current loop to make the input current follow a sinusoidal waveform. current amplifier receives il. detector output and multiplier (mul) output, subjects them to comparison and error amplification, and outputs the result to pmw comparator (pwm. comp). current amplifier is a transconductance amplifier the same as error amplifier. capacitance and resistance connected between output terminal (icmp) and gnd for phase compensation eliminate switching ripples of the input current. the current detector output is clamped to vclamp: 2.7 v by clamp circuit that constitutes an upper limit of voltage. (8) overcurrent protection circuit (ocp) ocp circuit is the circuit to detect the inductor current, and is to stop the output pulse to protect mosfet when detected current exceeds certain intensity. a detected voltage by sense resistor rs connected to gnd is inputted to the is pin, is converted by the il_detector which is an inverting amplifier, and is compared by overcurrent detection comparator. when is pin voltage lowers below a threshold value (ocp level), overcurrent protection circuit outputs a signal of an overcurrent status. the signal of overcurrent status resets a flip-flop for the out pulse, and then turns mosfet off. when is voltage gets near a threshold value, overcurrent protection circuit lowers the gain of multiplier (mul) to suppress the input current, thereby suppressing the audible noise of inductor attributable to an overcurrent. fig.12 current detector and overcurrent protection circuit fig.11 multiplier almost dc sinusoidal sinusoidal
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 18 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ ocp level is changed depending on the peak voltage of vdet pin by vin_detector as follows. while period a, ocp level is set to vocph (-0.4 v) because vdet pin voltage exceeds threshold voltage vvdeth (1.6 v). ocp level is changed only when vdet pin voltage is below vvdets (0.3v). at this time, the inductor current is low enough, and therefore will not abruptly change. further, if the load current is very low such vdet will not be below 0.3 v, the ocp level will not change over regardless of vdet. during period b, vdet will never go below threshold voltage vvdetl: 1.35 v. therefore, ocp level will not change either. some time in period c, vdet will be below threshold voltage vvdetl: 1.35 v, whereby ocp level is set to vocpl (-0.5 v). the same as period a, ocp level is changed only when vdet pin voltage is below vvdets (0.3 v). (9) undervoltage lockout circuit (uvlo) FA5612/13 has the uvlo circuit to avoid unexpected operation when the source voltage has dropped. the ic starts operation when the source voltage rising from zero has reached 9.6 v (typ.) for FA5612, or 13 v (typ.) for fa5613. after startup, each of ics stops operating when the source voltage has dropped to 9 v (typ.) while the ic stops a switching operation by uvlo circuit, the ic keeps out pin voltage low and further reduces ic consumption current t o b e l o w 1 0 0 a . (10) output circuit the output circuit consists of a push-pull circuit, directly drives mosfet. its maximum peak current is 1.5 a for sink, and 1.5 a for source. (11) zero current correction circuit unless multiplier output or current error amplifier input has offset voltage, the input current to converter will be almost zero when pfc converter has completely no load. however, if the offset voltage viewed from is pin is negative, the input current corresponding to offset voltage might flow to converter even when no load or light load. in such a case, the output voltage of power factor correction converter will rise abnormally because the input current will be excessive. offset voltage in the is pin (visof) is 0 mv. however, the offset voltage of the is pin against sense resistor voltage may be negative because a voltage will be generated by an external filter resistance connected to the is pin. therefore, FA5612/13 has this correction circuit to avoid rising the output voltage when light load with such case. usual output voltage from error amplifier is 0.5 v or higher. when its output voltage has dropped below 0.5 v, zero current correction circuit operates. error amplifier output voltage drops below 0.5 v when an input current flows under no or light load on account of offset in multiplier output or current error amplifier input. then, zero current correction circuit corrects the offset voltage of multiplier output. this function prevents the output voltage of power factor correction converter from rising excessively, so that the output voltage is kept at a constant level. the correction amount varies in a linear function of the output of current error amplifier, thereby ensuring a stable run. fig. 14 shows effects of zero current correction circuit. fig.13 overcurrent protection (ocp) level and vdet voltage vdet terminal voltage ocp level period a period b period c
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 19 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ consumption diagram of operations when is pin offset is negative input current ? o ? 0 r g R 1/2 X ? r a R 1/2 ? o ? X ? r a 0 r g X ? r a output voltage 0 ` R v o ` po X ? r a X ? r a without zero current correction circuit rated load a c i n p u t c u r r e n t no load current corresponding to offset time 1/2 cycle of ac input voltage with zero current correction circuit a c i n p u t c u r r e n t rated load no load effect by light load correction circuit time 1/2 cycle of ac input voltage fig.14 effects of zero current correction circuit output power po of power factor correction o u t p u t v o l t a g e v o o f p o w e r f a c t o r c o r r e c t i o n without zero current correction circuit with light load correction circuit
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 20 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 11. description of use for each pin (1) terminal no.1 (fb pin) functions (i) inputs feedback signal of output voltage setting (ii) detects fb pin open/short (iii) detects output overvoltage state applications (i) feedback signal input ? w i r i n g connect the node of dividing resistance for output voltage setting ? o p e r a t i o n the pfc output voltage is controlled so that the fb pin voltage will correspond to the internal reference voltage (2.5 v). for fb pin open circuit, fb pin is connected with pull-down resistance in ic inside. therefore, take its resistance into account when choosing the resistance of r1 and r2 to set the output voltage (vout). vref1rvref)rfb2r/()rfb2r(vout ? ? ? ? ? ? where: vref: reference voltage = 2.5 v (typ.) r f b : f b p i n p u l l - d o w n r e s i s t a n c e = 2 . 5 m ? ( t y p . ) to avoid an erratic operation by noises, connect capacitance c3 of 100 to 3300 pf between fb pin and gnd. (ii) fb pin open/short detection ? w i r i n g same as feedback signal input in (i) ? o p e r a t i o n when, on account of fb pin open circuit or short circuit of r2 in resistive divider, the fb input voltage has dropped below 0.3 v, the output of comparator (sp) is inverted, thereby stopping the ic output. (iii) output overvoltage detection ? w i r i n g same as feedback signal input in (i) ? o p e r a t i o n in normal operation, fb pin voltage is almost the same as reference voltage of error amplifier (2.5 v). like when the output voltage has risen for some reason, if the fb pin voltage reaches comparator reference voltage (1.09*vref), comparator (ovp) output is inverted to stop out pulses. as soon as output voltage returns to a normal level, out pulses are recovered. (2) terminal no.2 (vcmp pin) function (i) phase compensation of output of incorporated voltage error amplifier (erramp) application (i) phase compensation of incorporated erramp output ? w i r i n g connect r and c between comp and gnd as shown in fig. 16 ? o p e r a t i o n comp pin avoids an appearance of the double frequency ripple of the ac line on the fb pin voltage with connecting r and c. reference: example of applied circuit: c4 = 0.47 uf c5 = 2.2 uf r 3 = 1 0 k ? the above is an example. determine them upon sufficiently verifying your instrument. fig.16 vcmp pin circuit erramp 2 mul vcmp c4 r3 c5 fig.15 fb pin circuit 1 vcmp sp erramp vref(2.5v) vthfb(0.3v) fb vout r1 r2 open/short c3 rfb o.v.p static
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 21 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ besides, soft start function is realized by slowing a voltage rise of comp pin with adjustment of capacitance connected between comp and gnd. when starting, vcmp voltage rises and a switching operation starts at 0.5 v. at this time, mosfet on width increases gradually in proportion to the comp voltage rise. the soft start time is adjustable with adjustment with changing capacitors c4 and c5. i n c r e a s i n g c 4 , c 5 c a p a c i t a n c e p r o l o n g s s o f t s t a r t t i m e d e c r e a s i n g c 4 , c 5 c a p a c i t a n c e s h o r t e n s s o f t s t a r t t i m e (3) terminal no.3 (vdet pin) function (i) input voltage detection (multiplier input) application (i) input voltage setting for vdet pin multiplier generates current reference signal. its vdet pin (pin 3) receives sinusoidal full-waveform rectified waveforms. considering the dynamic range of multiplier operation, vdet pin peak value would be used within 0.65 to 2.4 v. therefore, set r6 and r7 in fig. 17 so that the peak voltage of sinusoidal waveforms at vdet pin will be between 0.65 and 2.4 v with the entire range of ac input voltage. recommended dividing ratio: r6:r7 = 160:1 caution: because multiplier has dispersions of characteristics, even if vdet pin voltage is 2.4 v or lower, multiplier might be saturated and the input peak current would slightly be truncated like trapezoidal waves. (4) terminal no.4 (is pin) functions (i) inductor current detection (ii) turn off out output upon detecting an overcurrent applications (i) via is pin, inductor current signal is applied to current error amplifier (cur_amp) that constitutes a current loop for making the input current follow sinusoidal waveforms. cur_amp that is connected with multiplier output receives current reference signal. is pin is current input terminal, and receives a potential of 0 to -0.4 v with respect to gnd level. (ii) when is pin voltage is lower than is threshold voltage, comparator output signal is inverted to turn off out output. ? s u p p l e m e n t when mosfet turns on, mosfet gate drive current and surge current are generated by discharge of stray capacitance, and then those currents flow to current detecting resistance rs. an excessively large surge current may cause an erratic operation to disturb the input current waveform. depending on the surge current intensity, timing, etc., pulse shoots may mix with turn-on parts of ic's out pulses. so, rc filter shown in fig. 18 is connected in generally. s i n c e t h e l e v e l i s d e t e r m i n e d b y r e s i s t i v e d i v i s i o n a s s h o w n i n f i g . 1 8 , 1 0 0 ? o r lower is recommended for input resistance r4. rated voltage at is pin for input of inductor current signal is -5 v. in case of a general boost circuit, a rush current flows for charging the output smoothing capacitance c2 the instant an ac input voltage has been connected. this current may be considerably greater than at a steady operation. as a result, is pin may receive a voltage that is far higher than usual. even if such ac voltage is connected, is pin must not be exposed to a potential higher than -5 v that is an absolute maximum rated voltage. there may be the case that a voltage higher than the rated is applied to is pin. in such case, it needs to use a preventive circuit for suppression of a rush current or to add the zener diode to is pin as shown in fig. 19. fig.19 is pin circuit (2) l1 d1 q1 rs 7 4 is gnd zd r4 c6 fa5610 c2 4 l1 d1 c1 q1 c2 is rs c6 r4 12k 28k 5v il detector fig.18 is pin circuit fig.17 vdet terminal circuit 3 c1 r6 r7 c6 vdet
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 22 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ caution: maximum power design it needs a notice about a setting of the sense resistance to output maximum power at whole input condition because a power limitation may occur by ic functions. fig. 20 shows a block diagram concerning the input current control. the vdet voltage is relatively high at high rms input voltage, and the input current is limited by ocp function shown in the path b of fig. 20 in such case. (reference figure is shown in fig. 21.) the vdet voltage is relatively low at the low rms input voltage, and the maximum output voltage of multiplier is low too. so, the input current is limited by the multiplier shown in the path a of fig. 20 in such case. (reference figure is shown in fig. 22.) this means that the maximum inductor current is limited by an above function unless the reasonable sense resistance is chosen. therefore, it needs to choose the sense resistor rs which satisfies each condition shown in the next page. note that the limitation of maximum inductor current is different as shown in fig. 23 according to whether by ocp or by multiplier. ? b y o c p : c u r r e n t p e a k s i n c l u d i n g s w i t c h i n g r i p p l e s a r e s u b j e c t e d t o l i m i t a t i o n . ? b y m u l t i p l i e r : c u r r e n t e x c l u d i n g s w i t c h i n g r i p p l e s i s s u b j e c t e d t o l i m i t a t i o n . fig.20 current control area block diagram fig.21 maximum inductor current at high input voltage fig.22maximum inductor current at low input voltage multiplier il detector 12k 28k vcm p cur. amp a b m_out m _out = k a b vdet icmp il_det is 5v icmp o.c.p osc pwm comp gate driver out a b multiplier il detector 12k 28k vcm p cur. amp a b m_out m _out = k a b vdet icmp il_det is 5v icmp o.c.p osc pwm comp gate driver out a b icmp current ?? ?? ocp ?c ?? ?_ ?n ?^ ?? ?? ?d ?? m a x i m u m i n d u c t o r c u r r e n t time ?? ?? ?c ?? ?_ ?n ?^ ?? ?? ?d ?? ocp ocp ? ?b ? ? ?o ? ?? ?z ? ?? ? ? ?3 ? ? ?b m a x i m u m i n d u c t o r c u r r e n t limited by multiplier before reaching ocp time ?g ?? ?? ?? ?c ?? ?_ ?n ?^ ?? ?? ?d ?? ocp ? ?? ? ? ? ( ?x ?c ?b ?` ?? ?o ?? ?b ?v ?? ? ?t ) ?? ?z ? ? ?? ? ? ? ( ?x ?c ?b ?` ?? ?o ?? ?b ?v ?? ? ? ? ? ) ?? ?? ?c ?? ?_ ?n ?^ ?d ?? i n d u c t o r c u r r e n t detail time m a x i m u m i n d u c t o r c u r r e n t time limitation by ocp (cover switching ripples) limitation by multiplier (do not cover switching ripples) fig.23 maximum current limitation fig.20 current control area block diagram
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 23 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ design current detecting resistance rs so as to meet a maximum power in the input voltage range, and also to clear 2 power limiting conditions below (fig. 24). (1) power limitation by multiplier design current detecting resistance rs so that vis voltage (mean) will be -0.33 v or greater that is maximum of item ? is pin voltage (vis_054) ?. i n c a s e o f s e t t l i n g a s o u t p u t p o w e r p o ( w ) , e f f i c i e n c y , a n d m i n i m u m i n p u t voltage vacmin (v), maximum inductor current iinmax (a) is given by following equation. ? vacmin po 2iinmax ? ? vis voltage (mean) will be -0.33 v or higher when: 0.33v vacmin po 2rs 0.33v-iinmaxrs ? ? ? ? ? ? ? t h e r e f o r e , d e s i g n c u r r e n t d e t e c t i n g r e s i s t a n c e r s ( ) s o a s t o m e a t : )( po2 vacmin0.33 rs ? ? ? ..... (1) (2) power limitation by ocp design current detecting resistance rs so that vis voltage (peak) will be -0.475 v or greater that is maximum of is threshold voltage (vocpl). in case of settling as ripple current iripple (a), switching frequency fsw, output voltage vout, boost inductance l, and on duty d, on duty d is given by following equation. vout minvac2vout d ? ? vis voltage (peak) will be -0.475 v or higher when: 0.475v) fsw2 dminvac2 vacmin po2 (rs 0.475v-) 2 iripple iinmax(rs ? ? ? ? ? ? ? ? ? ? ? ? ? t h e r e f o r e , d e s i g n c u r r e n t d e t e c t i n g r e s i s t a n c e r s ( ) s o a s t o m e a t : ? ? ? ? ? ? fsw2 dminvac vacmin po2 0.475 rs ( ) . . . . . ( 2 ) in order to output maximum power at a minimum input voltage, therefore, select rs determined by expression (1) or (2), whichever smaller. caution: to define a current limitation by multiplier, select the voltage at vdet pin so as to be 0.54 v or higher even at a minimum input voltage. fig.24 maximum power limitation vis v) vdet v) vis_054 (-0.33vmax) vocpl (-0.475vmax) vis( ? vis( ` \ ^ ????? 0.54v vis (mean) vis (peak) (1) by multiplier (2) by overcurrent threshold
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 24 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ (5) terminal no. 5 (icmp pin) function (i) phase compensation for output of incorporated current error amplifier (cur_amp) application (i) phase compensation for output of incorporated cur_amp ? w i r i n g connect r and c between icmp and gnd as shown in fig. 25. ? o p e r a t i o n r and c are connected to icmp pin to block ripple components of switching frequency that could otherwise appear on is pin input. (reference) example of applied circuit: c8 = 100 pf c9 = 680 pf r 8 = 4 7 k ? the above is an example. determine them upon sufficiently verifying your instrument. (6) terminal no. 6 (gnd pin) function constitutes the reference of each part of ic. (7) terminal no. 7 (out pin) functions (i) drives mosfet (ii) sets oscillation frequency applications (i) drive of mosfet ? w i r i n g connected via resistance ro to gate terminal of mosfet ? o p e r a t i o n goes high when mosfet is turned on. nearly vcc voltage is outputted. goes low when mosfet is turned off. voltage of nearly 0 v is outputted. ? s u p p l e m e n t connect a gate resistance for current limitation at out pin, prevention of oscillation of gate terminal voltage, etc. rated output currents of ic: source ... 1.5 a, sink ... 1.5 a. connection in fig. 27 or 28 allows to distinctly set the gate drive currents for turning on and off mosfet. (ii) setting of oscillation frequency ? w i r i n g (1) ordinary connection connect resistance rg between mosfet gate and gnd if no buffer is connected on ic output as shown in fig. 26, 27 and 28. according to resistance rg, switching frequency can be selected out of 3 different modes given in table below. resistance rg accuracy temperature characteristics mode1 frequency diffusion 4 . 7 k 5 % m a x 2 0 0 p p m / c m a x 1 2 k 2 % m a x 2 0 0 p p m / c m a x mode2 65khz fixed 1 3 k 5 % m a x 2 0 0 p p m / c m a x m o d e 3 6 0 k h z f i x e d 2 7 k 5 % m a x 2 0 0 p p m / c m a x * r o : 1 0 0 ? m a x . caution: ? r e s i s t a n c e r o b e t w e e n o u t p i n a n d f e t g a t e m u s t b e 1 0 0 ? o r l e s s ? i f m o d e 3 i s s e l e c t e d ( 2 7 k ? u s e d ) , s t a r t i n g u p t h e f r e q u e n c y s e t t i n g r a i s e s t h e o u t - g n d v o l t a g e u p t o 1 . 4 v fig.25 icmp pin circuit cur_amp 5 pwm_comp icmp c8 r8 c9 fig.27 out pin circuit (2) fig.28 out pin circuit (3) fig.26 out pin circuit (1)
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 25 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ (2) if buffer is connected on ic output if buffer is connected on ic output, select a configuration shown in fig. 29, and select the frequency setting resistance as given in table below. resistance rg accuracy temperature characteristics m o d e 1 j i t t e r i n g 4 . 7 k 5 % m a x 2 0 0 p p m / c m a x m o d e 2 6 5 k h z f i x e d 1 3 k 5 % m a x 2 0 0 p p m / c m a x m o d e 3 6 0 k h z f i x e d 3 0 k 5 % m a x 2 0 0 p p m / c m a x * r o : 1 0 0 ? m a x . i f c o m b i n e d r e s i s t a n c e c o n n e c t e d o n b u f f e r o u t p u t i s r x , s e t r x t o 3 k ? o r h i g h e r t a k i n g into account dispersion and temperature characteristics. example: s e l e c t r 1 1 = 1 0 ? , a n d r 1 2 = 1 0 k ? . s u p p o s e t h e i r r e s i s t a n c e m a y c h a n g e b y 1 0 % m a x i m u m o n a c c o u n t o f t h e i r d i s p e r s i o n a n d temperature characteristics. if 3 of them each are connected in parallel, r x = 1 0 . 0 1 k ? 9 0 % 3 = 3 . 0 0 3 k ? holds, thereby clearing the requisite. caution: ? r e s i s t a n c e r o b e t w e e n o u t p i n a n d b u f f e r m u s t b e 1 0 0 ? o r l e s s ? i f m o d e 3 i s s e l e c t e d ( 3 0 k ? u s e d ) , s t a r t i n g u p t h e f r e q u e n c y s e t t i n g r a i s e s t h e o u t - g n d v o l t a g e u p t o 1 . 2 v ? a b o v e c o n d i t i o n s p r e s u p p o s e h fe of transistor used in buffer is 50 minimum, and that vbe is 0.3 v maximum taking the temperature characteristics into account. unless characteristics of a particular transistor to use clear the requisites, set the frequency resorting to a method in ?(3) other circuit configuration.? (3) other circuit configuration unless the circuit configuration connected to out pin clears the specifications in (1) nor (2), determine the frequency based on the current and voltage defined by specified frequency setting. ( see p. 15 fig. 5 frequency setting circuit ) be sure to take into account the ic characteristics, and dispersion and temperature characteristics of parts connected to out pin. general precaution about frequency setting: in setting the frequency, make sure, in addition to respecting our recommendations in (1) and (2) above, there is no problem of influences by dispersion and temperature characteristics of your resistors, wiring, noise (influence of auxiliary power supply that operates before pfc starts, in particular) and other matters than resistance itself based on the current and voltage regarding the specified frequency setting. in setting of the frequency, please confirm whether there is no bad influence of following items including our setting recommendation and our setting specification. - dispersion of or the temperature characteristic of resistance used, a design of wiring, noise (especially from sub power supply before the pfc start operation), etc. vcc ro rg r11 r12 r21 r22 out ?? ?? ?? ?r rx 7 fig.29 buffer combined resistance rx
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 26 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ (8) terminal no. 8 (vcc pin) function (i) supplies ic with power application (i) supplies ic with power ? w i r i n g connect a startup resistance between rectified voltage line and vcc pin. generally, connect a rectified and smoothed voltage from auxiliary winding provided on transformer. or connect an external dc source. ? o p e r a t i o n at the time of startup in case vcc voltage is obtained from auxiliary winding, the current via the startup resistance charges the smoothing capacitance and, when the level rises up to uvlo on threshold voltage, ic starts up. immediately before startup, a current of at least 110 ua (max.) that is a startup current for ic must be fed. during a steady operation, vcc is supplied from inductor's auxiliary winding (fig. 30). as the source voltage rises from zero, the operation starts at 9.6 v (typ.) for FA5612, or at 13 v (typ.) for fa5613. any of started-up ics stops operating when the source voltage drops down to 9 v (typ.) while ic stops operation by under voltage lockout circuit, out pin keeps low level and shuts the output of power supply off. supplement: under voltage lockout function avoids an erratic operation of circuit when source voltage has dropped. noise applied to vcc pin will cause an erratic operation. to avoid the noise, connect a capacitance near vcc pin whether ic is operated by another source or not. determine the capacitance so that the noise generated on vcc pin will be within 0.6 v, and make doubly sure no erratic operation occurs by noise (fig. 31). fig.30 vcc pin circuit (1) 8 vcc fig.31 vcc pin circuit (2) 8 vcc dc ? external dc source
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 27 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 12. advice for design (1) advice in pattern designing main circuit mosfet, inductor, diodes, etc. perform switching under high voltage and large current. if wiring of ic or signals inputted to ic gets too near such main circuit parts, they may operate erratically upon being affected by noise generated there. attention must be paid particularly in following cases (examples of faulty cases). ? i c i s a r r a n g e d u n d e r i n d u c t o r o r o t h e r m a i n c i r c u i t p a r t s , o r i m m e d i a t e l y b e h i n d main circuit parts on double sided circuit board (fig. 32) ? i c i s a r r a n g e d c l o s e t o i n d u c t o r , m o s f e t o r d i o d e ( f i g . 3 3 ) ? s i g n a l w i r i n g i s p l a c e d u n d e r i n d u c t o r o r n e a r m o s f e t o r d i o d e ( f i g . 3 4 ) (2) typical gnd wiring in ic area to minimize influences on ic of noises from main circuit, separate gnd of ic and signal lines for parts of ic area, and gnd of pfc main circuit away from each other, and connect them via one point near current detecting resistance rs and output capacitance. is signal whose voltage level is low is liable to noise. minimize lengths of is pin-rs and rs-gnd wiring. arrange vcc-gnd capacitance close to ic. otherwise, the effect will be poor. arrange the capacitance between ic area input terminal and gnd close to ic. it also has a function of noise elimination and, if away from ic, it will be affected by noise. caution: wiring is exemplified for you to understand how to connect the gnd line. noise and incidental erratic operations differ from one instrument to another. adopting any wiring exemplified in fig. 35 will not necessarily guarantee normal operations of your instruments. fig.32 example of inadvisable arrangement (1) ( Y ic ic is arranged under inductor (or on immediately opposite side on circuit board) fig.33 example of inadvisable arrangement (2) mosfet ic ic is arranged close to inductor or mosfet mosfet ? ^ fig.34 example of inadvisable pattern signal wiring passes under inductor or close to mosfet
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 28 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ fig.35 example of advisable gnd wiring fbvcmpvdetis vccoutgndicmp FA5612 /fa5613 rs fig.36 example of inadvisable gnd wiring (gnd is common to signal line parts and main circuit) ` r l fbvcmpvdetis vccoutgndicmp FA5612 /fa5613 rs fig.37 example of inadvisable gnd wiring (liable to noise when turning on if gnd is common to vcc capacitance and signal line) fig.38 example of gnd wiring (gnd of vcc capacitance is distinct from signal line gnd) drive current when turning on drive current when turning on
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 29 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ (3) precautions in use regarding terminal noise if noise is applied to any ic pin, an erratic operation may be caused. proceed to design upon respecting the precautions below. condition pin malfunction in fear input regulations cautions in design switching may stop when noise is over over voltage protection level ic may become stanbay mode when noise is under short detection level fb offset occurs in output voltage and output voltage rises or falls input signal is only for feedback voltage of output voltage connect condenser near terminal pin output of multiplier output becomes unstable, and input current waveform may disturbed switching may become when noise is over threshold voltage vcmp switching may stop when noise is under threshold voltage cancel noise confirm sufficiently phase compensation constant vdet output of multiplier output becomes unstable, and input current waveform may be disturbed cancel noise connect condensor near pin current may be detected incorrectly is it may turn off when noise is over overcurrent protection level cancel noise connect condensor near pin icmp because a duty changes, input current waveform may be disturbed cancel noise confirm sufficiently phase compensation constant gnd reference voltage changes, ic may not behave normally cancel noise ground wiring should be a wide wiring out the output may fall not to be able to drive mos normally when signals more than the ability of the driver are input cancel noise - input noise (within absolute maximum ratings) vcc ic may stop when noise under uvlo is input don't input noise under uvlo when moving connect condensor near pin fb vcmp vdet icmp vcc a parasitism element works, and the malfunction such as ic stop may occur is ic may be destroyed out ic may be destroyed input minus voltage (less than absolute maximum voltage) vcc a parasitism element works, and the malfunction such as ic stop may occur don't input minus voltage less than maximum absolute voltage - fb vcmp vdet icmp ic may be destroyed is gnd level may be changed out input plus voltage (more than absolute maximum voltage) vcc ic may be destroyed don't input minus voltage more than maximum absolute voltage -
.0.08 an-049j rev.1.0 an-054e rev.1.2 apr.-2011 30 fa561 2 , fa561 3 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor/ 13. example of application circuit ( 390v / 1.5a output )

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